AP Subject A Essentials 1: Binary, Two's Complement, and Bit Operations

AP Subject A · Installment 1 · An independent study resource for the 2026 exam and Syllabus Ver.7.2. It is not affiliated with IPA and does not guarantee a pass. Open the series hub

This lesson begins with the habit of not assigning a value to a bit string too soon. Understanding radix conversion, two’s complement (2の補数), overflow (オーバフロー), masks, and shifts as one system prepares you for variations in wording. The 2026 exam uses the name Subject A (科目A); the official past question below is identified by its historical Morning (午前) section. Passing Subject A alone does not mean passing the entire AP exam.

Learning goals

Distinguish bit width, signedness, mathematical values, and stored bit patterns.
Convert binary, hexadecimal, and binary fractions and calculate representation ranges.
Form and decode negative numbers in two’s complement.
Distinguish carry from signed overflow.
Apply AND, OR, XOR, NOT, logical shifts, and arithmetic shifts correctly.

First rule: identify three things

Before calculating, ask:

What is the bit width?
Is the quantity signed or unsigned?
Are you handling a mathematical value or a stored bit pattern?

For example, the same 8-bit pattern 11110000 is 128+64+32+16=240 as an unsigned integer. As a signed two’s-complement integer, it is 240-256=-16. A bit string alone does not determine its value.

Binary, hexadecimal, and fractions

Add the positional weights.

00101101₂ = 32+8+4+1 = 45
Grouping binary digits in fours gives 1010 1101₂ = AD₁₆: 1010₂=A₁₆ and 1101₂=D₁₆.
Fractional places have weights 2^-1, 2^-2, 2^-3, ..., so 0.101₂ = 1/2+1/8 = 0.625.
10.101₂ = 2+1/2+1/8 = 2.625.

A finite decimal fraction is not necessarily finite in binary. For example, decimal 0.1 repeats in binary, so storing it in a limited number of bits produces an approximation.

Ranges and two’s complement

For n bits, the ranges are:

Unsigned: 0..2^n-1
Two’s complement: -2^(n-1)..2^(n-1)-1

The signed 8-bit range is therefore -128..127. Because the positive side has one fewer value, the negation of -128, namely +128, cannot be represented in the same 8-bit format.

Forming `-13`

Start with 8-bit +13.

00001101   (+13)
11110010   (invert every bit)
11110011   (add 1 → -13)

To check in reverse, read 11110011 as unsigned 243 and calculate 243-256=-13. Inversion alone gives 11110010, or 242, and 242-256=-14. You must add 1 after inversion.

Carry is not signed overflow

A carry is a bit leaving the fixed width. Signed overflow means that the true mathematical result lies outside the signed range.

In 8 bits, 127+1 gives 01111111+00000001 = 10000000. The stored pattern reads as -128, so this is signed overflow.
-1+1 gives 11111111+00000001 = 1 00000000. The stored 8-bit result is 00000000, or 0. There is a carry but no signed overflow.

In two’s-complement addition, signed overflow occurs when two inputs with the same sign produce a result with the opposite sign. Adding operands with opposite signs cannot cause signed overflow because the sum lies between the operands.

Bit masks

A mask retains, sets, or toggles selected bits. Applied to the low four bits of 10110110:

10110110 AND 00001111 = 00000110   # retain only the low four bits
10110110 OR  00001111 = 10111111   # set the low four bits
10110110 XOR 00001111 = 10111001   # toggle the low four bits

NOT inverts every bit, so its width must be explicit. The 8-bit NOT of 00001101 is 11110010; the 16-bit NOT is 1111111111110010.

Logical and arithmetic shifts

For right shifts, determine which bits enter the vacated positions.

Logical right shift of 8-bit 11110000 by 2: 00111100 = 60
Arithmetic right shift of the same pattern by 2 as a signed 8-bit value: 11111100 = -4

This arithmetic-right result assumes two’s complement and replication of the most significant sign bit. For negative values, an arithmetic right shift and integer division can differ depending on the language and its rounding rule. Check the question or language specification.

It is also unsafe to memorize left shift as unconditionally “multiply by 2.” In an ordinary fixed-width whole-bit-pattern left shift, outgoing high bits are discarded and zeros enter on the right. In signed 8-bit form, shifting 50 (00110010) left once gives representable 100 (01100100). Shifting 100 (01100100) left once gives 11001000, which reads as 200-256=-56 in signed 8-bit form. The mathematical value 200 is outside the range.

Japanese exam questions may define 算術左シフト as a question-specific operation that preserves the sign bit and shifts only the remaining bits left. Do not assume that this is the same as a whole-bit-pattern shift or a programming language’s left shift. Follow the definition in the question.

Check your reasoning with an official past question

The following is a faithful English translation with formatting adapted from the IPA’s publicly released question. It appeared in the historical Morning section of the Autumn 2021 Applied Information Technology Engineer Examination.

A CPU has a 16-bit operation register. When signed 16-bit integers x1 and x2 are added using 16-bit signed addition (x1+x2), which condition guarantees that the addition result will not overflow for every combination of x1 and x2? Here, |x| denotes the absolute value of x, and negative numbers are represented in two’s complement.

ア When |x1|+|x2|≤32,768

イ When both |x1| and |x2| are less than 32,767

ウ When x1×x2>0

エ When x1 and x2 have different signs

出典：令和3年度秋期応用情報技術者試験午前問8

Answer: エ

ア: Incorrect. 32,767+1=32,768 satisfies |x1|+|x2|≤32,768, but exceeds the signed 16-bit maximum of 32,767.
イ: Incorrect. In 32,766+32,766=65,532, both absolute values are below 32,767, but the result is out of range.
ウ: Incorrect. A positive product means the operands have the same sign—the situation in which overflow can occur. For example, 20,000+20,000=40,000 is out of range.
エ: Correct. The sum of numbers with opposite signs lies between the two operands. Since both operands are already within -32,768..32,767, the sum stays in range.

Five original diagnostic questions

The questions below are original practice questions, not IPA questions. Choose an answer first, then check every option.

1. What is the value of `0.101₂`?

ア 0.5 / イ 0.625 / ウ 0.75 / エ 1.25

Answer: イ. 1/2+0/4+1/8=0.625.

ア: This omits the final 1, worth 1/8.
イ: This correctly adds the positional weights.
ウ: This is 0.11₂ = 1/2+1/4 = 0.75.
エ: This misapplies the fractional place values.

2. Which is the 8-bit two’s-complement representation of `-13`?

ア 00001101 / イ 11110010 / ウ 11110011 / エ 10001101

Answer: ウ. Invert 00001101, then add 1 to obtain 11110011.

ア: This is +13.
イ: This omits the addition of 1 after inversion; 242-256=-14.
ウ: This is correct because 243-256=-13.
エ: This confuses sign-and-magnitude with two’s complement. In two’s complement it is 141-256=-115.

3. Which operation keeps only the low four bits of `10110110`?

ア AND 00001111 / イ OR 00001111 / ウ XOR 00001111 / エ AND 11110000

Answer: ア. It clears the high four bits and preserves the low four.

ア: The result is 00000110, retaining only the low four bits.
イ: The result is 10111111, setting every low bit to 1.
ウ: The result is 10111001, toggling every low bit.
エ: The result is 10110000, retaining the high four bits instead.

4. What results from an arithmetic right shift of signed 8-bit `11110000` by 2?

ア 00111100 / イ 11111100 / ウ 11000000 / エ 11111000

Answer: イ. Filling twice with sign bit 1 gives 11111100, or -4.

ア: This is a logical right shift by 2, with zeros entering.
イ: This correctly replicates the sign bit.
ウ: This is the result of shifting the whole 8-bit pattern left by 2.
エ: This is an arithmetic right shift by only 1.

5. Which signed 8-bit addition overflows?

ア -1+1 / イ 60+60 / ウ 100+40 / エ -64+(-64)

Answer: ウ. 100+40=140 exceeds 127. Its stored pattern is 10001100, which reads as 140-256=-116 when signed.

ア: The result 0 is in range. There is a carry but no signed overflow.
イ: The result 120 is in range.
ウ: The mathematical result 140 is out of range, so this overflows.
エ: The result -128 is the signed 8-bit minimum and is representable.

Common mistakes

Assigning a value before checking width and signedness.
Inverting the bits for two’s complement but forgetting +1.
Treating every carry out of the top bit as signed overflow.
Failing to check whether a right shift fills with zero or the sign bit.
Assuming every fixed-width left shift means multiplication by 2.
Mixing a question’s special definition of 算術左シフト with a language’s shift rules.

Quick review and review schedule

A bit string’s meaning comes from its width, signedness, and interpretation. Form a negative two’s-complement value by inverting and adding 1, and judge signed overflow separately from carry. AND retains masked bits, OR sets them, XOR toggles them, and shifts require both a fill rule and attention to the fixed-width range.

Review this material the same day → the next day → after 3 days → after 7 days. This spaced-review schedule is separate from the publication cadence of the series. Visit the AP Subject A series hub for the overall sequence. The next core article will cover logic and sets; there is no link to it before publication.