2026 Applied Information Technology Engineer Exam Subject A 007 — CPU, Cache, and Performance Calculations

• Revised: 2026-10-20
• Source checked: 2026-10-20
• Scope: 2026 IPA Applied Information Technology Engineer Examination (AP), Subject A, syllabus Ver.7.2

Disclaimer: IPA may change the exam format and scope. Always check official IPA materials before the exam. This is an independent study resource; IPA has not reviewed or endorsed it. All questions here are original questions, not past exam questions.

0. Learning index

1. Terminology table (KO/JA/EN)
2. CPU performance: clock period, CPU cycles, execution time
3. Weighted average CPI (instruction mix)
4. Cache: hit/miss rate and effective access time (two conventions)
5. Pipeline: the ideal k-stage model and its limits
6. Five original practice questions (answers, derivations, wrong-choice explanations)
7. Quick sheet
8. Common traps
9. Final self-check
10. 1/3/7-day review suggestion
11. Sources and syllabus mapping

1. Terminology table

KO	JA	EN
클록 주파수	クロック周波数	clock frequency
클록 주기(사이클 타임)	サイクルタイム（クロック周期）	clock period (cycle time)
CPI(명령당 평균 사이클 수)	CPI（1命令当たりの平均クロック数）	CPI (cycles per instruction)
명령 수	命令数	instruction count
명령 믹스	命令ミックス	instruction mix
CPU 시간(실행 시간)	CPU時間（実行時間）	CPU time (execution time)
MIPS	MIPS	MIPS
히트율 / 미스율	ヒット率 / ミス率	hit rate / miss rate
히트 시간	ヒット時間	hit time
미스 페널티	ミスペナルティ	miss penalty
실효(평균) 접근 시간	実効アクセス時間	effective (average) access time, AMAT
명령 파이프라인	命令パイプライン	instruction pipeline
파이프라인 해저드	パイプラインハザード	pipeline hazard
데이터/구조/제어 해저드	データ/構造/制御ハザード	data/structural/control hazard
스톨 / 플러시	ストール / フラッシュ	stall / flush
지연 시간 / 처리량	レイテンシ / スループット	latency / throughput

2. CPU performance calculations

2.1 Assumptions (apply to every formula)

• CPU time model: we compute only the time the CPU spends executing instructions. Whole-system elapsed time (I/O waits, OS, other processes, etc.) is not inferred from these formulas.
• CPI is an average: it is the average CPI for the given instruction mix. If the mix changes, CPI changes.
• Same workload: unless stated otherwise, we compare the same program with the same instruction count.
• Units: 1 GHz = 10^9 cycles/s, 1 MHz = 10^6 Hz, 1 ns = 10^-9 s, Hz = 1/s.
• No conclusions from clock alone: different instruction set architectures (ISAs) lead to different instruction counts and CPIs, so clock frequency alone cannot show which CPU is superior.

2.2 Formulas and units

Formula	Units
Clock period T = 1 / f	s = 1 / (cycles/s) → s/cycle
CPU cycles = instruction count × CPI	instructions × (cycles/instruction) = cycles
Execution time = instruction count × CPI / f = CPU cycles × T	cycles / (cycles/s) = s

2.3 Mandatory worked example

Given: f = 2.4 GHz, instruction count = 1.2×10^9, average CPI = 1.5

1. Clock period: T = 1 / (2.4×10^9 /s) ≈ 4.167×10^-10 s ≈ 0.417 ns
2. CPU cycles: 1.2×10^9 instructions × 1.5 cycles/instruction = 1.8×10^9 cycles (the instruction unit cancels)
3. Execution time: 1.8×10^9 cycles / (2.4×10^9 cycles/s) = 0.75 s (the cycle unit cancels, leaving s)
4. Check: 1.8×10^9 cycles × (1/2.4×10^9) s/cycle = 0.75 s

2.4 A caution about MIPS

MIPS = f / (CPI × 10^6). For the example above, 2.4×10^9 / (1.5 × 10^6) = 1600 MIPS. However, MIPS depends on the instruction set and the instruction mix. Because different ISAs need different numbers of instructions to do the same work, MIPS is not a reliable performance ranking metric across different architectures.

3. Weighted average CPI

3.1 Formula

Weighted CPI = Σ (fraction of instruction class i × CPI_i), where the fractions sum to 1 (unit: cycles/instruction)

3.2 Example

Given: instruction count = 2.0×10^9, f = 2.0 GHz

Instruction class	Fraction	CPI	Fraction × CPI
Arithmetic (ALU)	0.5	1	0.5
Load/store	0.3	2	0.6
Branch	0.2	3	0.6
Total	1.0	—	1.7

• Weighted CPI = 1.7 cycles/instruction
• CPU cycles = 2.0×10^9 × 1.7 = 3.4×10^9 cycles
• Execution time = 3.4×10^9 cycles / (2.0×10^9 cycles/s) = 1.7 s
• Independent check (sum of cycles per class): 1.0×10^9×1 + 0.6×10^9×2 + 0.4×10^9×3 = 1.0×10^9 + 1.2×10^9 + 1.2×10^9 = 3.4×10^9 cycles ✓
• Caution: the simple average of CPIs (1+2+3)/3 = 2.0 ignores the fractions and is wrong.

4. Cache: effective access time

4.1 Definitions

• Hit rate h: the fraction of accesses found in the cache (0 ≤ h ≤ 1)
• Miss rate = 1 − h
• Percent → probability: 95% = 95/100 = 0.95, miss rate = 1 − 0.95 = 0.05. Always plug values between 0 and 1 into the formulas.

4.2 Two conventions (never mix them)

Convention A — hit time is included on every access

AMAT = hit time + miss rate × miss penalty

• Miss penalty = the additional time spent after a miss is detected (ns)
• Model: every access first checks the cache (hit time), and only misses add the penalty.

Convention B — weighted average of total latencies

Effective access time = h × hit latency + (1 − h) × miss total latency

• Miss total latency = the entire time of one access when it misses (ns)

Conversion: miss total latency = hit time + additional miss penalty. After this conversion the two conventions give the same value. Plugging Convention A’s “additional penalty” into Convention B’s “total latency” slot, or vice versa, is wrong.

4.3 Mandatory worked example

Given: hit time 2 ns, hit rate 95%, additional miss penalty 60 ns

• Probability conversion: h = 0.95, 1 − h = 0.05
• Convention A: 2 ns + 0.05 × 60 ns = 2 + 3 = 5 ns
• Convert to Convention B: miss total latency = 2 + 60 = 62 ns 0.95 × 2 ns + 0.05 × 62 ns = 1.9 + 3.1 = 5 ns
• Both conventions agree at 5 ns. Units: (dimensionless probability) × ns = ns.

In exam questions, read the wording to decide whether the “main-memory access time on a miss” is an additional amount or a total. If you cannot tell, state which convention you assumed.

5. Pipeline

5.1 Assumptions of the ideal k-stage pipeline

• k stages, every stage takes the same time t
• no stalls or flushes, no hazards
• zero latch (register) overhead between stages
• n instructions executed back-to-back

5.2 Formulas

Item	Formula	Units
Non-pipelined time	n × k × t	ns
Pipelined time	(k + n − 1) × t	ns
Latency of one instruction	k × t (not reduced even in the ideal model)	ns
Steady-state throughput	approaches 1/t	instructions/ns

Meaning of (k + n − 1): the first instruction needs k×t to pass through all k stages (fill), then the remaining n − 1 instructions complete one every t. The drain period, as the last instruction leaves the pipeline, is also included in this formula.

5.3 Example

Given: k = 5, t = 2 ns, n = 100

• Non-pipelined: 100 × 5 × 2 ns = 1000 ns
• Pipelined: (5 + 100 − 1) × 2 ns = 104 × 2 = 208 ns
• Speedup: 1000 / 208 ≈ 4.81× (less than k = 5)
• Latency of one instruction: 5 × 2 = 10 ns (unchanged by pipelining)
• Steady-state throughput: 1/t = 0.5 instructions/ns = 5×10^8 instructions/s

Latency vs throughput: pipelining raises the number of instructions completed per unit time (throughput); it does not shorten the time one instruction takes from start to finish (latency). In the ideal model the speedup only approaches k as n grows; it is not always equal to k.

5.4 Real-world limits

• Fill/drain: when n is small, the fixed (k − 1)t cost is a larger share.
• Data hazard: a later instruction needs the result of an earlier one and must wait.
• Structural hazard: two instructions try to use the same hardware resource (e.g. a memory port) at once.
• Control hazard: the next instruction cannot be fixed until a branch outcome is known.
• Stall/flush: hazards insert empty cycles (bubbles) or discard wrongly fetched instructions.
• Unequal stages: the clock must match the slowest stage, so t = maximum stage time.
• Latch overhead: register time between stages is added, so adding more stages does not keep increasing the benefit indefinitely.

6. Original practice questions (5)

All questions below were written new for this article. They are original questions, not IPA past exam questions.

Question 1 (original) — CPU time and units

A CPU runs at 2.5 GHz. A program has 3.0×10^9 instructions and average CPI 2.0. What is the CPU execution time? (CPU time model, same workload)

• A. 0.6 s
• B. 1.2 s
• C. 2.4 s
• D. 2400 s

Answer: C

Derivation: cycles = 3.0×10^9 × 2.0 = 6.0×10^9 cycles. Time = 6.0×10^9 cycles / (2.5×10^9 cycles/s) = 2.4 s.

• A (0.6 s): divided by CPI instead of multiplying — 3.0×10^9 / (2.0 × 2.5×10^9).
• B (1.2 s): ignored CPI and computed only instruction count / f.
• D (2400 s): converted GHz as if it were MHz (10^6) — 6.0×10^9 / 2.5×10^6.

Question 2 (original) — Weighted CPI

The instruction mix is class X 60% (CPI 1), class Y 30% (CPI 3), class Z 10% (CPI 5). With 1.0×10^9 instructions and a 1.0 GHz clock, which pair gives the weighted CPI and the CPU execution time?

• A. CPI 3.0, 3.0 s
• B. CPI 2.0, 2.0 s
• C. CPI 2.0, 0.5 s
• D. CPI 1.0, 1.0 s

Answer: B

Derivation: fractions sum 0.6 + 0.3 + 0.1 = 1.0 (checked). Weighted CPI = 0.6×1 + 0.3×3 + 0.1×5 = 0.6 + 0.9 + 0.5 = 2.0. Cycles = 1.0×10^9 × 2.0 = 2.0×10^9. Time = 2.0×10^9 / 1.0×10^9 /s = 2.0 s.

• A: used the simple average (1+3+5)/3 = 3.0 — ignores the fractions.
• C: CPI is right, but time was wrongly computed as instruction count / (CPI × f).
• D: used only the CPI of class X, the most frequent class.

Question 3 (original) — Cache convention

Hit time is 1 ns, hit rate is 90%, and the total latency of one access on a miss is 51 ns (including the hit-check time). What is the effective access time?

• A. 6.0 ns
• B. 5.9 ns
• C. 6.1 ns
• D. 46.0 ns

Answer: A

Derivation: h = 0.90, 1 − h = 0.10. Convention B: 0.90 × 1 + 0.10 × 51 = 0.9 + 5.1 = 6.0 ns. Check with Convention A: additional penalty = 51 − 1 = 50 ns, 1 + 0.10 × 50 = 6.0 ns.

• B (5.9 ns): put the additional penalty 50 ns into the Convention B formula instead of the total latency — 0.9 + 5.0. The hit-check time on a miss is lost.
• C (6.1 ns): put the total latency 51 ns into the Convention A formula as the additional penalty — 1 + 5.1. The hit time is counted twice.
• D (46.0 ns): swapped h and 1 − h — 0.10 × 1 + 0.90 × 51.

Question 4 (original) — Ideal pipeline timing

An ideal 4-stage pipeline (no stalls, no overhead) has every stage time equal to 5 ns. How long does it take to execute 20 instructions?

• A. 100 ns
• B. 115 ns
• C. 120 ns
• D. 400 ns

Answer: B

Derivation: (k + n − 1) × t = (4 + 20 − 1) × 5 = 23 × 5 = 115 ns.

• A (100 ns): computed only n × t — ignored the fill period (k − 1)t = 15 ns.
• C (120 ns): computed (k + n) × t — forgot to subtract 1.
• D (400 ns): the non-pipelined time n × k × t.

Question 5 (original) — Assumptions and limits

Which statement is correct?

• A. A CPU with a higher clock frequency always finishes any program faster, regardless of ISA.
• B. In an ideal k-stage pipeline, the latency of one instruction is reduced from k×t to t.
• C. MIPS values can directly compare the performance of CPUs with different ISAs.
• D. If instruction count and clock frequency are the same, CPU time decreases in proportion to CPI as the average CPI decreases.

Answer: D

Derivation: CPU time = instruction count × CPI / f, so with instruction count and f fixed, CPU time ∝ CPI.

• A: different ISAs change instruction count and CPI, so clock alone cannot decide. Also, the CPU time model says nothing about whole-system elapsed time.
• B: pipelining only raises throughput; even in the ideal model one instruction’s latency stays k×t.
• C: MIPS depends on the instruction set and instruction mix, so it is unreliable for comparing different ISAs.

Answer key

Question	1	2	3	4	5
Answer	C	B	A	B	D

7. Quick sheet

• T = 1/f (s); 2.4 GHz → ≈ 0.417 ns
• Cycles = instruction count × CPI
• CPU time = instruction count × CPI / f (s)
• Weighted CPI = Σ fraction_i × CPI_i (Σ fractions = 1)
• MIPS = f / (CPI × 10^6) — depends on ISA and mix
• Convention A: AMAT = hit time + (1 − h) × additional miss penalty
• Convention B: h × hit latency + (1 − h) × miss total latency, where miss total latency = hit time + additional penalty
• Non-pipelined n·k·t, pipelined (k + n − 1)·t, latency k·t, throughput → 1/t
• Mandatory example answers: 1.8×10^9 cycles, 0.75 s / cache 5 ns (both conventions)

8. Common traps

1. Converting GHz as MHz (confusing 10^9 and 10^6).
2. Dividing by CPI instead of multiplying.
3. Computing weighted CPI as a simple average.
4. Not checking that the fractions sum to 1.
5. Plugging in 95 for a 95% hit rate (convert to 0.95).
6. Mixing Convention A’s additional penalty with Convention B’s total latency.
7. Dropping the (k − 1)t fill period from pipeline time.
8. Believing “pipelining always gives exactly k× speedup” or “it makes a single instruction faster”.
9. Ranking CPUs with different ISAs by clock or MIPS alone.
10. Mistaking CPU time for whole-system elapsed time.

9. Final self-check

• I can derive 1.8×10^9 cycles and 0.75 s for 2.4 GHz, 1.2×10^9 instructions, CPI 1.5, with unit cancellation.
• I can compute weighted CPI and execution time for a mix whose fractions sum to 1, and verify via per-class cycle sums.
• I can distinguish Conventions A and B and get 5 ns both ways for hit 2 ns, hit rate 95%, additional penalty 60 ns.
• I can explain (k + n − 1)t in terms of fill/drain and distinguish latency from throughput.
• I can say why the three hazards, stalls/flushes, unequal stages, and latch overhead break the ideal model.
• I can explain why no conclusion can be drawn from MIPS or clock alone.

10. Review suggestion

• Day 1: using only the quick sheet, recompute the three mandatory examples (CPU time, weighted CPI, cache) on a blank page.
• Day 3: redo the five original questions with derivations hidden, and explain aloud which mistake produces each wrong choice.
• Day 7: make one new question of each type by changing the numbers (e.g. a different hit rate, different k and n), and review the ten common traps.

11. Sources and syllabus mapping

• Official source: IPA “応用情報技術者試験（レベル3）シラバス Ver.7.2” https://www.ipa.go.jp/shiken/syllabus/omgdg50000005kq5-att/syllabus_ap_ver7_2.pdf (checked 2026-10-20, PDF pages 14–16)
• Mapping (syllabus headings verbatim):
  • 大分類2：コンピュータシステム／中分類3：コンピュータ構成要素 › 1. プロセッサ › （8）プロセッサの性能 → Sections 2 and 3, Questions 1, 2, 5
  • 大分類2：コンピュータシステム／中分類3：コンピュータ構成要素 › 1. プロセッサ › （9）プロセッサの高速化技術 → Section 5, Questions 4, 5
  • 大分類2：コンピュータシステム／中分類3：コンピュータ構成要素 › 2. メモリ › （5）メモリの容量と性能 → Section 4, Question 3
  • 大分類2：コンピュータシステム／中分類3：コンピュータ構成要素 › 2. メモリ › （3）メモリシステムの構成と記憶階層 → scope reference only (cache mapping and write policies come in a later installment)
• The syllabus defines scope only. The formulas, examples, and questions here are this article’s own explanations; no external sources or past exam questions were used.