Hardware, Circuits, Measurement, and Control

Disclaimer: This is unofficial study material for Subject A of the IPA Applied Information Technology Engineer Examination (AP). It is not affiliated with IPA and does not guarantee exam scope or question trends. Always confirm current information with official IPA materials. All five practice questions below are original questions; no past exam questions were used.

Learning index

• AP Subject A 02: Logic expressions and truth tables — logic basics (not retaught here)
• AP Subject A 07: CPU architecture — role of adders/registers in the CPU, memory hierarchy (not repeated here)
• AP Subject A 11: Hardware, Circuits, Measurement, and Control ← this article

Syllabus mapping (Ver.7.2)

Major / middle category	Item	Covered in this installment
1 Basic theory / 1 Basic theory	3. Information theory (2) Coding theory	analog vs digital, sampling, quantization, A/D conversion
1 Basic theory / 1 Basic theory	5. Measurement and control theory (1) Signal processing	sampling theorem, A/D and D/A conversion
1 Basic theory / 1 Basic theory	5. (2) ① Control concepts and mechanisms	feedback/feedforward, open/closed loop, response characteristics, control stability, PWM control
1 Basic theory / 1 Basic theory	5. (2) ② Sensors and actuators	sensor detects → computer decides → actuator produces mechanical action
2 Computer systems / 3 Computer components	1. Processor (5), (6)①	role of adders/registers (brief link), half/full adders, sequential vs combinational circuits
2 Computer systems / 3 Computer components	2. Memory (1)	RAM/ROM, DRAM/SRAM, refresh, flash memory, volatile/nonvolatile
2 Computer systems / 6 Hardware	1. (1) Electric/electronic circuits	combinational vs sequential logic, XOR, flip-flops, timing charts
2 Computer systems / 6 Hardware	1. (2) Machinery and control	open loop, closed loop, feedback control, PWM control
2 Computer systems / 6 Hardware	1. (3) ④ Embedded system components	sensors, actuators, memory, A/D and D/A converters

Terminology table

한국어	日本語	English
조합회로	組合せ回路	combinational circuit
순서회로	順序回路	sequential circuit
전가산기	全加算器	full adder
반가산기	半加算器	half adder
자리올림(캐리)	桁上げ（キャリー）	carry
배타적 논리합	排他的論理和（XOR）	exclusive OR (XOR)
플립플롭	フリップフロップ	flip-flop
클록 / 상승 에지	クロック／立上りエッジ	clock / rising edge
타이밍 차트	タイミングチャート	timing chart
휘발성 / 비휘발성	揮発性／不揮発性	volatile / nonvolatile
리프레시	リフレッシュ	refresh
표본화(샘플링)	標本化（サンプリング）	sampling
표본화 정리	標本化定理（サンプリング定理）	sampling theorem
에일리어싱	エイリアシング（折返し雑音）	aliasing
안티에일리어싱 저역통과 필터	アンチエイリアシング用ローパスフィルタ	anti-aliasing low-pass filter
양자화 / 양자화 오차	量子化／量子化誤差	quantization / quantization error
센서 / 액추에이터	センサー／アクチュエーター	sensor / actuator
오픈루프 / 클로즈드루프	オープンループ／クローズドループ	open loop / closed loop
피드백 제어	フィードバック制御	feedback control
목표값 / 측정값(제어량) / 편차	目標値／制御量（測定値）／偏差	setpoint / measured value / error
제어기 / 제어대상(플랜트)	調節部（コントローラ）／制御対象	controller / plant
PWM(펄스폭 변조) / 듀티비	PWM（パルス幅変調）／デューティ比	PWM (pulse-width modulation) / duty cycle

1. Combinational vs sequential circuits

• Combinational circuit: outputs depend only on the current inputs. There is no internal state (memory). Examples: full adder, decoder, multiplexer.
• Sequential circuit: outputs depend on the current inputs and the internal state (past history). It contains storage elements (such as flip-flops), and the state usually changes in step with a clock. Examples: register, counter, shift register.
• A timing chart plots the 0/1 changes of the clock, inputs, and outputs along a time axis. For sequential circuits, the key is reading “which value is captured at which clock edge.”
• In real circuits, inputs must be stable for a certain time just before and after the clock edge (setup and hold times); otherwise correct operation is not guaranteed. Exam questions usually assume these are met.

2. Flip-flop: a 1-bit storage element

A flip-flop is the basic storage element of sequential circuits and stores 1 bit. The positive-edge-triggered D flip-flop used here captures the value of D at the instant of the rising edge (clock 0→1) into Q, and holds Q until the next rising edge. Even if D changes between edges, Q does not change. A register is a group of such flip-flops side by side.

3. Semiconductor memory essentials only

Type	Storage principle (typical)	Refresh	When power is removed
SRAM	bistable (flip-flop-type) cell	not required	contents lost (volatile)
DRAM	charge on a capacitor	required (charge leaks, so it is periodically rewritten)	contents lost (volatile)
ROM / flash memory	—	—	contents retained (nonvolatile)

• For the exam it is enough to distinguish “DRAM needs refresh,” “SRAM is also volatile,” and “flash memory is nonvolatile.”
• Speed/capacity and memory-hierarchy comparisons belong to AP Subject A 07 and are not repeated here.

4. A/D conversion: sampling → quantization → coding

1. Sampling: take values of the continuous-time signal at fixed intervals (sampling frequency fs).
2. Quantization: map each sample to one of a finite number of levels. The difference produced is the quantization error.
3. Coding: express the level number as an N-bit binary code. N bits can represent 2^N codes.

Sampling theorem: if a signal is band-limited to a maximum frequency fmax, it can in theory be reconstructed when fs > 2·fmax (strictly “greater than”). The boundary value fs = 2·fmax is not a safe choice; in practice a margin is used. fs/2 is called the Nyquist frequency.

Aliasing: frequency components above fs/2 fold back into lower frequencies after sampling and become indistinguishable from the original signal. To prevent this, an anti-aliasing low-pass filter (LPF) is placed before the ADC (in the analog stage) to attenuate components at or above fs/2 in advance. They cannot be removed digitally after sampling.

5. Sensors, actuators, and feedback control

• Sensor: converts a physical quantity such as temperature, light, distance, or pressure into an electrical signal.
• Actuator: converts an electrical signal into mechanical motion, heat, etc. (DC servo motor, stepping motor, solenoid, heater, etc.).
• Open-loop control: operates as predetermined without feeding back the measured result. It cannot correct for disturbances. (Sequence control, which proceeds through predetermined steps, is a typical example.)
• Closed-loop (feedback) control: compares the measured value with the setpoint to obtain the error, and acts in the direction that reduces the error. This is negative feedback.
• Feedforward control: measures a disturbance in advance and compensates before its effect appears.
• Elements: setpoint r, measured value y, error e, controller, actuator, plant, sensor.
• PWM control: adjusts average power by changing the fraction of ON time within a fixed period (duty cycle). ON time = period × duty cycle.
• Stability caution: feedback is only a structure that tries to reduce the error; it does not by itself guarantee stability. With excessive gain or large delay (dead time), overshoot, oscillation (hunting), or divergence can occur. Response characteristics (speed, overshoot, steady-state error) and stability must be examined together.

6. Examples A–E

Example A: Full adder

Definition: S = A XOR B XOR Cin, Cout = AB + Cin(A XOR B). (XOR = exclusive OR, AB = A AND B, + = OR)

A	B	Cin	A XOR B	S	AB	Cin(A XOR B)	Cout
0	0	0	0	0	0	0	0
0	0	1	0	1	0	0	0
0	1	0	1	1	0	0	0
0	1	1	1	0	0	1	1
1	0	0	1	1	0	0	0
1	0	1	1	0	0	1	1
1	1	0	0	0	1	0	1
1	1	1	0	1	1	0	1

Check: in every row, A+B+Cin (decimal) = 2·Cout + S (e.g., 1+1+1 = 3 = 2·1 + 1).

Trace A=1, B=1, Cin=0: A XOR B = 0 → S = 0 XOR 0 = 0. AB = 1 → Cout = 1 + 0·0 = 1. That is, 1+1+0 = 2 = (10)₂.

A full adder is a combinational circuit, so its outputs are determined only by the current inputs (A, B, Cin); previous inputs have no effect.

Example B: Positive-edge-triggered D flip-flop

Assumptions: initial Q = 0. D is stable just before each rising edge (setup and hold times met). No asynchronous reset/set inputs are used. Propagation delay is ignored.

Rising edge	1	2	3	4
D just before edge	1	0	1	1
Q just after edge	1	0	1	1

• Q becomes [1, 0, 1, 1] just after the edges and holds that value between edges. Even if D changes between edges, Q does not change until the next rising edge.
• Contrast: in a combinational circuit the output follows the input immediately (after only the delay), with no notion of “holding.” A D flip-flop stores state, so it is a sequential circuit.

Example C: Sampling and data size

Assumptions: the analog signal is band-limited to fmax = 3 kHz. Mono (1 channel), 12 bits/sample, no headers or compression, duration 2 s. Units: kB = 1,000 B (decimal), KiB = 1,024 B (binary).

1. Theoretical condition: fs > 2·fmax = 6 kHz (strict inequality).
2. Choice: fs = 8 kHz → 8 kHz > 6 kHz, so the condition is met (with margin).
3. Samples: 8,000 samples/s × 2 s = 16,000 samples.
4. Bits: 16,000 × 12 bit = 192,000 bit.
5. Bytes: 192,000 ÷ 8 = 24,000 B = 24 kB (decimal).
6. Binary units: 24,000 ÷ 1,024 = 23.4375 KiB.

If components above 3 kHz (e.g., noise) are present, components above fs/2 = 4 kHz fold back into lower frequencies and can cause aliasing, so an analog anti-aliasing LPF is placed before the ADC.

Example D: Quantization (10-bit, [0, 5 V))

Convention (used consistently in this article): an ideal unipolar ADC. The input range [0, 5 V) (0 V included, 5 V excluded) is divided into 2^10 = 1,024 uniform bins. Code k represents the bin [kΔ, (k+1)Δ), with its representative level at the bin center (k+½)Δ, so each input is mapped to the nearest level. Clipping, noise, and nonlinearity are excluded.

• Quantization step: Δ = 5/1,024 V = 0.0048828125 V = 4.8828125 mV
• Maximum quantization error (nearest-level): Δ/2 = 2.44140625 mV
• Code for Vin = 2.50 V: floor(2.50/Δ) = floor(2.50 × 1,024 / 5) = floor(512) = 512 (2.50 V is the lower boundary of bin 512 and belongs to bin 512 under the [ , ) convention)

Note: there is also a convention Δ = 5/(2^10 − 1) that aligns the endpoints 0 V and 5 V with codes 0 and 1,023, but this article does not mix it in. When solving a question, check the convention stated in the question first.

Example E: Feedback control and PWM

Assumptions: temperature controlled by a heater. Setpoint r = 25 °C, measured value y = 22 °C. Error convention e = r − y. When the error is positive, the controller outputs more heating. PWM period 20 ms, duty cycle 25%. Ideal switching assumed.

• Error: e = 25 − 22 = +3 °C (3 °C below the setpoint).
• Signal flow: sensor → ADC → controller → PWM/driver → heater (actuator) → plant (room/device) → sensor (back around the loop).
• e > 0 → more heating → y rises → e decreases: the action reduces the error, so this is negative feedback.
• PWM: ON time per period = 20 ms × 0.25 = 5 ms (OFF 15 ms). This only sets the average supplied power; it does not guarantee reaching 25 °C or stability.
• Contrast with open loop: running only at “fixed 25% duty” without feeding back the measured value cannot correct for disturbances such as changes in outside temperature.
• Stability: if the gain is too large or sensor/heat-transfer delay is large, the system can oscillate around the setpoint or become unstable.

7. Links to earlier installments (brief)

• AP2 (logic expressions and truth tables): the XOR/AND/OR expressions and truth-table reading for the full adder use AP2’s tools directly. They are not retaught here.
• AP7 (CPU): the adder in the CPU’s ALU is full adders chained for the word width, and a register is a group of flip-flops. See AP7 for CPU structure and memory hierarchy.

8. Quick sheet

• Combinational = current inputs only / sequential = inputs + state (memory)
• S = A⊕B⊕Cin, Cout = AB + Cin(A⊕B)
• D-FF (rising edge): D at the edge → Q, held between edges
• SRAM: bistable cell, no refresh, volatile / DRAM: capacitor, refresh required, volatile / ROM, flash: nonvolatile
• Sampling theorem: fs > 2·fmax, anti-aliasing LPF before the ADC
• Data size (bit) = fs × duration × bits/sample × channels (no headers/compression)
• kB = 1,000 B, KiB = 1,024 B
• [0, V) into 2^N bins: Δ = V/2^N, max error (nearest level) = Δ/2
• e = r − y, PWM ON time = period × duty cycle
• Negative feedback ≠ guaranteed stability (watch gain and delay)

9. Common traps

1. Computing the full-adder S with OR (1, 1, 0 → wrongly S = 1).
2. Thinking a D-FF’s Q follows D even between edges (confusing it with a latch/combinational circuit).
3. Reading the D-FF output one edge late (confusing it with the next stage of a shift register).
4. Judging fs = 2·fmax as “sufficient” (ignoring the strict inequality).
5. Forgetting ÷8 when converting bits to bytes, or confusing kB and KiB.
6. Mixing the 5/2^10 and 5/(2^10−1) conventions when computing Δ.
7. Taking the maximum quantization error as Δ (under the nearest-level convention it is Δ/2).
8. Reversing the error sign convention (r − y).
9. Confusing the ON time at 25% duty with the OFF time.
10. Asserting “feedback is always stable.”

10. Practice questions (5 original)

All questions were newly written for this article and are original questions. No past exam questions were used.

Q1. A full adder is defined by S = A XOR B XOR Cin, Cout = AB + Cin(A XOR B). Which output is correct for A = 1, B = 1, Cin = 0?

• ア S = 0, Cout = 0
• イ S = 0, Cout = 1
• ウ S = 1, Cout = 1
• エ S = 1, Cout = 0

Q2. A positive-edge-triggered D flip-flop starts with Q = 0. The values of D just before four successive rising edges are [1, 0, 1, 1] (setup/hold times met, no asynchronous inputs used). Which describes Q correctly?

• ア Q just after each edge is [0, 1, 0, 1].
• イ Q just after each edge is [1, 0, 1, 1], and between edges Q immediately follows changes in D.
• ウ Q just after each edge is [1, 0, 1, 1], and between edges Q holds its previous value.
• エ Q just after each edge is [1, 1, 1, 1].

Q3. An analog signal band-limited to fmax = 3 kHz is A/D-converted at fs = 8 kHz for 2 seconds, mono, 12 bits/sample (no headers or compression, kB = 1,000 B). Which is correct?

• ア 16,000 samples; data size 192,000 bytes
• イ 8,000 samples; data size 12,000 bytes
• ウ 16,000 samples; data size 23.4375 kB
• エ 8 kHz > 6 kHz, so the sampling theorem condition is met; 16,000 samples; data size 24,000 bytes (24 kB)

Q4. An ideal 10-bit unipolar ADC divides the input range [0, 5 V) into 2^10 uniform bins and maps each input to the nearest level (clipping, noise, and nonlinearity excluded). Which gives the correct quantization step Δ and maximum quantization error?

• ア Δ ≈ 4.883 mV, max error ≈ 2.441 mV
• イ Δ ≈ 4.888 mV, max error ≈ 2.444 mV
• ウ Δ ≈ 4.883 mV, max error ≈ 4.883 mV
• エ Δ = 0.5 V, max error = 0.25 V

Q5. In heater temperature control, setpoint r = 25 °C, measured value y = 22 °C, and error e = r − y. The signal flow is sensor → ADC → controller → PWM/driver → heater → plant → sensor, and heating increases when e is positive. With PWM period 20 ms and duty cycle 25%, which is correct?

• ア e = −3 °C, and the ON time per period is 5 ms.
• イ e = +3 °C, and the ON time per period is 15 ms.
• ウ e = +3 °C, and the ON time per period is 5 ms. Negative feedback tries to reduce the error but does not by itself guarantee stability.
• エ e = +3 °C, and the ON time per period is 5 ms. Because it is negative feedback, convergence to 25 °C without oscillation is guaranteed.

11. Answers and explanations

Question	1	2	3	4	5
Answer	イ	ウ	エ	ア	ウ

Q1 (answer イ)

• ア ✗ Drops the carry from 1+1. Since AB = 1, Cout = 1.
• イ ✓ A XOR B = 0, S = 0 XOR 0 = 0. Cout = AB + Cin(A XOR B) = 1 + 0 = 1.
• ウ ✗ Computes S with OR (1 OR 1 OR 0 = 1) instead of XOR.
• エ ✗ Swaps the values of S and Cout (in 1+1 = (10)₂ the carry is Cout).

Q2 (answer ウ)

• ア ✗ Reads Q just before each edge (the previous value) as the output, delaying by one edge. A D-FF outputs that edge’s D on Q just after that edge.
• イ ✗ The post-edge values are right, but the claim that Q follows D between edges is wrong. That is the behavior of a transparent latch (or a combinational circuit).
• ウ ✓ Captures D at each rising edge to give [1, 0, 1, 1] and holds until the next edge.
• エ ✗ Assumes Q stays 1 once it becomes 1. D = 0 just before the 2nd edge, so Q becomes 0.

Q3 (answer エ)

• ア ✗ 192,000 is the number of bits. It omits ÷8 and mislabels the result as bytes.
• イ ✗ Does not multiply by the 2-second duration (counts only 1 second).
• ウ ✗ 23.4375 is the value in KiB (1,024 B units). In decimal kB it is 24 kB.
• エ ✓ fs = 8 kHz > 2 × 3 kHz = 6 kHz. 8,000 × 2 = 16,000 samples, × 12 = 192,000 bit = 24,000 B = 24 kB.

Q4 (answer ア)

• ア ✓ Δ = 5/1,024 V = 4.8828125 mV ≈ 4.883 mV; max error Δ/2 = 2.44140625 mV ≈ 2.441 mV.
• イ ✗ Mixes in the endpoint convention 5/(2^10 − 1) = 5/1,023 V. The stated convention divides [0, 5 V) into 1,024 bins.
• ウ ✗ Takes the maximum error as Δ (the value for a truncation convention). With nearest-level mapping it is Δ/2.
• エ ✗ Divides by the bit count 10 instead of 2^10.

Q5 (answer ウ)

• ア ✗ Computes the error as y − r, giving the opposite sign. The convention is e = r − y = +3 °C.
• イ ✗ 15 ms is the OFF time (75%). The ON time is 20 ms × 0.25 = 5 ms.
• ウ ✓ e = +3 °C, ON time 5 ms. Negative feedback is a structure that reduces error, but stability depends on gain, delay, etc.
• エ ✗ The error and ON time are right, but “guaranteed stable convergence” is wrong. Excessive gain or large delay can cause oscillation or instability.

12. Self-check

• I can explain the difference between combinational and sequential circuits in terms of “state (memory).”
• I can reproduce all 8 rows of the full-adder truth table from the formulas.
• I can read Q just after each edge and the hold between edges from a D-FF timing chart.
• I can distinguish refresh and volatility for SRAM, DRAM, and ROM/flash.
• I can explain fs > 2·fmax and where the anti-aliasing LPF goes (before the ADC).
• I can convert data size correctly from bit → B → kB / KiB.
• I can state the convention behind Δ = V/2^N and max error Δ/2.
• I can compute the sign of e = r − y and the PWM ON time, and explain why feedback does not guarantee stability.

13. Review plan

• After 1 day: without looking at the quick sheet, rewrite the full-adder formulas/truth table and the D-FF trace.
• After 3 days: redo Examples C and D with changed numbers (e.g., fmax = 4 kHz, 16 bits) and check the units.
• After 7 days: re-solve the five practice questions and explain in one line why each wrong option is wrong.

Sources

• IPA “応用情報技術者試験（レベル3）シラバス Ver.7.2” https://www.ipa.go.jp/shiken/syllabus/omgdg50000005kq5-att/syllabus_ap_ver7_2.pdf (checked: 2026-10-21)
• All practice questions are original; no past exam questions were used.